1. Field of the Invention
The present invention generally relates to managing free memory space and more particularly to managing multiple memory banks in multiple memory channels.
2. Description of the Related Art
In general, memory managers are utilized to manage the allocation and de-allocation of available memory space (i.e., free memory space) in a memory device, such as RAMs, DRAMs, and the like. More particularly, the addresses of free memory space are typically stored as entries on a free list, which is stored on the memory device. A conventional memory manager allocates and de-allocates free memory space in the memory device by reading and writing entries from the free list. A conventional memory manager also generally includes a buffering and/or caching system to copy the free list or a portion of the free list to a buffer and/or cache.
One conventional buffering/caching system for a memory manager is a ring buffer. In a ring buffer, the head (i.e., the highest address) and the end (i.e., the lowest address) of the buffer are linked together. A read pointer and a write pointer are typically used to read and write to the buffer from the head to the end of the buffer. When these pointers reach the end of the buffer, they are directed back to the head of the buffer.
One disadvantage of conventional memory managers, such as those that use a ringer buffer, is that the memory device is accessed each time entries are read or written from the buffer. This can reduce the speed and efficiency of the memory device as well as the hardware and/or software system accessing the memory device.
In accordance with one aspect of the present invention, free memory can be managed by creating a free list having entries with addresses of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold.
In accordance with another aspect of the present invention, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.